This invention relates to a converting circuit and bandwidth management apparatus in a mixed network obtained by mixing an STM and ATM networks. More particularly, the invention relates to a converting circuit for converting time division multiplexed frames to ATM cells or ATM cells to time division multiplexed frames, and to an ATM switch bandwidth management apparatus for managing the bandwidth of STM calls.
Recent progress in ATM (Asynchronous Transfer Mode) technology has been remarkable and some ATM switch networks have been constructed. Nevertheless, replacing all presently existing STM (Synchronous Transfer Mode) switch networks is not possible because of the costs involved and, for the time being, STM and ATM networks will continue to be used together. However, there is little doubt that use of ATM, which is advantageous in terms of transferring large quantities of data, will gradually increase and that ATM will become the mainstay of switching networks. A problem encountered when two types of networks, namely STM and ATM switch networks, are used together is that dual transmission lines must be provided. This is wasteful of equipment. Accordingly, an important problem to be solved in the future involves a method of sending data from an STM network to an ATM network and vice versa.
FIG. 17 shows an example of a time division multiplexed frame used in an STM network. This is an example in which one frame period T has been partitioned into n (e.g., 64) time slots TS1xcx9cTS64. Here a maximum of 64 channels of data can be time division multiplexed into the time slots TS1xcx9cTS64. Twenty frames construct a subframe. Each item of channel data is composed of eight bits (one byte) and has a bit rate of 8xc3x978 K=64 (Kbps) per time slot, where 8 KHz is associated with one frame.
FIG. 18 is a diagram useful in describing the format of a cell in an ATM network An ATM cell is composed of a 5-byte cell header HD and a 48-byte payload PLD. The header HD includes (1) a generic flow control (GFC) used in flow control between links, (2) a virtual path identifier (VPI) for specifying a path, (3) a virtual channel identifier (VCI) for call identifying purposes, (4) payload type (PT), (5) cell loss priority CLP and (6) header error control (HEC).
With the proliferation of ATM networks, it has become essential to be able to access an ATM network from an ATM network and vice versa, and therefore an arrangement through which such mutual access can be performed is necessary. For example, if an STM network is to send data to an ATM network, the time division multiplexed frames of FIG. 17 must be converted to ATM cells of the kind shown in FIG. 18. If an ATM network is to send data to an STM network, then ATM cells must be converted to time division multiplexed frames.
Furthermore, it is required that cells output from an STM switch satisfy a 64-Kbps data bandwidth, which is a feature of an STM network. Accordingly, in an ATM network, basically it is required to establish a path based upon a 64-Kbps CBR (Constant Bit Rate), to arrange it so that the CTD (Cell Transfer Delay) in the ATM switch is small and to absorb cell fluctuation.
Further, an important factor in bandwidth control, which is a feature of an ATM switch, is to arrange it so that there is no change even if an STM switch is accommodated. In other words, since QOS (Quality of Service) control of CBR (Constant Bit Rate), ABR (Available Bit Rate) and VBR (Variable Bit Rate) in an ATM switch is performed collectively within the switch, it is better that special processing for an STM switch not be executed. That is, it is so arranged that the bandwidth management algorithm of the ATM switch be employed even if there is a path connection request from the STM switch. If this arrangement is adopted, an advantage gained is that a path connection request from an STM switch can be handled in a manner equivalent to that of a path connection request from another ATM terminal.
The bandwidth used between STM switches varies depending upon traffic. For this reason, it is preferred that the path connection between STM switches be based upon an SVC (Switched Virtual Channel). However, if another ATM terminal accommodated by an ATM switch uses the entire bandwidth in a case where a path is connected by the SVC service, a CBR path will no longer be established for an STM switch. Accordingly, dedicated bandwidth is reserved for the path between STM switches and a PVC (Permanent Virtual Circuit) is established between the STM switches within the limits of the dedicated bandwidth. However, since it wasteful if dedicated bandwidth is not used, it is necessary to reduce such waste by varying dedicated bandwidth dynamically in dependence upon daily traffic.
Accordingly, a first object of the present invention is to realize a mixed network of ATM and STM networks by providing a converting circuit for converting time division multiplexed frames of an STM network to cells of an ATM network and a converting circuit for converting ATM cells to time division multiplexed frames.
A second object of the present invention is to realize a mixed network of ATM and STM networks in which fluctuation of cells in an ATM network is absorbed and a bit rate of 64 Kbps is satisfied in an ATM network.
A third object of the present invention is to realize a mixed network of ATM and STM networks adapted to minimize waste of bandwidth by varying dedicated bandwidth between STM switches dynamically in dependence upon one day of traffic of an STM switch, and to accept STM calls to the greatest extent possible.
A fourth object of the present invention is to realize a mixed network of ATM and STM networks in which when the total bandwidth of an accepted STM call exceeds the dedicated bandwidth between STM switches, decides whether or not to accept an STM call based upon whether or not any surplus bandwidth remains (i.e., bandwidth other than the dedicated bandwidth).
According to the present invention, the first object is attained by,providing a converting circuit for converting a time division multiplexed frame of an STM network, which frame is the result of time division multiplexing n channels in one frame and one byte of data in each channel, to cells of an ATM network, each cell having a header and an m-byte payload, comprising (1) a time switch memory having, for each destination STM switch, a storage area possessing m consecutive addresses, (2) a control memory for storing a corresponding relationship between time slot numbers in a time division multiplexed frame and addresses of the time switch memory, (3) means for writing data of each time slot in the time division multiplexed frame to a storage area of the time switch memory that is specified by the corresponding relationship stored in the control memory, (4) a buffer memory for storing data read out of the time switch memory, (5) means for reading data out of the time switch memory successively, storing the data in the buffer memory and reading the data out of the buffer memory successively in m-byte units, and (6) cell generating means for generating a cell in which m bytes of consecutive data read out of the buffer memory is adopted as a payload and a header having an identifier conforming to a destination STM switch is added onto the payload. Thus, the converting circuit makes it possible to convert a time division multiplexed frame to cells.
According to the present invention, the first object is attained by providing a converting circuit for converting a time division multiplexed frame of an STM network, which frame is the result of time division multiplexing n channels in one frame and one byte of data in each channel, to cells of an ATM network, each cell having a header and an m-byte payload, comprising (1) a destination memory for storing correspondence between time slot numbers of a time division multiplexed frame and STM switches that are destinations, (2) a destination add-on unit for adding onto data in the time slots of the time division multiplexed frame the destinations of the corresponding time slots that have been stored in the destination memory, (3) a routing unit, to which the time division multiplexed frame having the added-on destinations is input, for disassembling the data of the frame on a per-address basis and outputting the disassembled data, (4) a buffer, which is provided for each destination, for storing the disassembled data output by the routing unit, and (5) cell generating means for generating a cell in which m-byte data read out of each buffer in consecutive fashion is adopted as a payload and a header having an identifier conforming to a destination is added onto the payload. Thus, the converting circuit makes it possible to convert a time division multiplexed frame to cells.
According to the present invention, the first object is attained by providing a converting circuit for converting ATM network cells each having a header and an m-byte payload to time division multiplexed frames of an STM network, wherein one frame is composed of n channels and each channel is composed of one byte, comprising (1) a buffer for storing m bytes of payload data, which construct the payload of a received cell, in such a manner that a cell number and a payload number are capable of being identified, (2) a time switch memory in which time slot numbers serve as addresses, (3) a control memory for storing correspondence between combinations of cell numbers and payload numbers and addresses of the time switch memory, (4) writing means for identifying cell number and payload number of payload data that has been read out of the buffer, obtaining from the control memory an address that corresponds to a combination of the cell number and payload number and writing this payload data to a storage area of the time switch memory that is specified by this address, and (5) means for reading data out of the time switch memory consecutively in the order of the time slot numbers and converting the data to a time division multiplexed frame. Thus, the converting circuit makes it possible to convert a time division multiplexed frame to cells.
According to the present invention, the second object is attained by arranging it so that payload data of a plurality of received cells can be stored in the buffer, providing readout timing management means for managing timing at which the payload data of each cell is read out of the buffer, and reading prescribed payload data out of the buffer at the readout timing.
According to the present invention, the third object is attained by providing a bandwidth management apparatus of an ATM switch in a mixed network of STM and ATM networks, comprising means for establishing a PVC of a prescribed bandwidth between each of the STM switches in advance, means for monitoring traffic between the STM switches, and PVC bandwidth adjusting means for adjusting the bandwidth of the PVC in dependence upon the traffic between the STM switches. Thus, in accordance with the bandwidth management apparatus of the present invention, the PVC bandwidth between STM switches can be varied dynamically in dependence upon one day of STM switch traffic. As a result, wasting of bandwidth can be minimized and STM calls can be accepted to the maximum extent possible.
According to the present invention, the fourth object is attained by providing a bandwidth management apparatus of an ATM switch having means for accepting a call in response to a call establishment request from an STM switch if the PVC bandwidth has enough margin, checking bandwidth other than the PVC bandwidth if the PVC bandwidth has insufficient margin, accepting the call if the bandwidth other than the PVC bandwidth has enough margin and refusing the call if the bandwidth other than the PVC bandwidth has insufficient margin. If this arrangement is adopted, an ATM bandwidth management algorithm is applied even in response to a path connection request from an STM switch, whereby a path connection request from an STM switch can be handled in a manner equivalent to that of a path connection request from another ATM terminal.